Pipeline Processor
Q31.
Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format. OP Ri, Rj, Rk where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri. I1: ADD R1, R2, R3 I2: MUL R7, R1, R3 I3: SUB R4, R1, R5 I4: ADD R3, R2, R4 I5: MUL R7, R8, R9 Consider the following three statements. S1: There is an anti-dependence between instructions l2 and l5 S2: There is an anti-dependence between instructions l2 and l4 S3: Within an instruction pipeline an anti-dependence always creates one or more stalls Which one of above statements is/are correct?Q32.
Suppose the functions F and G can be computed in 5 and 3 nano seconds by functional units U_{F} and U_{G}, respectively. Given two instances of U_{F} and two instances of U_{G}, it is required to implement the computation F(G(X_{i})) for 1\leq i\leq 10. Ignoring all other delays, the minimum time required to complete this computation is ________ nanoseconds.Q33.
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency calledQ35.
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instructions is ______.Q36.
The stage delays in a 4-stage pipeline are 800,500,400 and 300 picoseconds.The first stage (with delay 800 picoseconds)is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds.The throughput increase of the pipeline is ________ percent.Q37.
Consider a 5- segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline)Q38.
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor isQ39.
Consider the following reservation table for a pipeline having three stages S1,S2 and S3. The minimum average latency (MAL) is ________.